Study programme 2019-2020Français
Digital Electronics
Learning Activity
CodeLecturer(s)Associate Lecturer(s)Subsitute Lecturer(s) et other(s)Establishment
I-SEMI-003
  • VALDERRAMA SAKUYAMA Carlos Alberto
      • Université de Mons
      Language
      of instruction
      Language
      of assessment
      HT(*) HTPE(*) HTPS(*) HR(*) HD(*) Term
      AnglaisAnglais2622000Q1

      Description of the modifications to the Q3 2019-2020 online assessment procedures (Covid-19)
      Individual online multiple-choice written test divided into theoretical and practical questions during the exam period.
      Theoretical questions (weighting 60%) Content: Digital circuits, types, technologies and design steps. Complementary MOS gates. Building static CMOS logic gates. Switch logic. Delay estimation. Layout considerations. Size optimizations. Regular structures. Synchronous circuits.  Memories. Arithmetic operators.
      Practical questions (40% weighting): documentation available on Moodle. Analysis/understanding of code examples and electrical diagrams. Content: VHDL programming. Design techniques. Basic digital circuits. Synchronous and asynchronous circuits. Control. Design for test.
       

      Content of Learning Activity

      This course is a free adaptation of the digital courses of circuits of professors Rabaey and Weste. The adaptation accounts of recent progress in the field of micro-electronics, stressed by the dominant influence of CMOS technology compared to the bipolar one. This course shows the development of the digital circuits from the base, from transistors and logical gates to the description of complex blocks (combinational and sequential circuits, adders, memories, multiplieurs). It includes the development of VLSI circuits, showing methodologies and tools necessary for the design and test of current digital circuits. Practical sessions are based on using the VHDL language at the RT (Register Transfert) level and FPGA-based design tool to come up with dedicated digital circuits. Laboratory sessions cover the design flow from basic gates design to memories and RTL components down to IC (Integrated Circuits) layout using Cadence and Mentor EDA tools.  

      Required Learning Resources/Tools

      Various information available on the students computer-assisted learning site: notes, slides, previous years tests (sometimes solved), tests in line (QCM) allowing the students to be evaluated, bonds useful, electronic tools CAD, complementary presentations and web links. Technical documentation, datasheets, user manual, and specifications. Electrical interconnection of electronic components (schemes). Previous years' achievements (technical reports, source code, video).    

      Recommended Learning Resources/Tools

      Digital Integrated Circuits: A Design Perspective. Jan M. Rabaey, Anantha P. Chandrakasan, Borivoje Nikolić. 2003. Pearson Education. 761 pages. ISBN 0130909963. Modern VLSI Design: IP-Based Design (4th Edition), Wayne Wolf, Prentice Hall, ISBN-13: 978-0137145003.  

      Other Recommended Reading

      Weste and Eshraghian, "Principles of VLSI Design - A Systems Perspective" 2ed. Cmos Vlsi Design: A Circuits and Systems Perspective. Neil H. E. Weste, David Harris. 2005. Pearson/Addison-Wesley. 967 pages. ISBN 0321149017 Weste, Harris, "CMOS VLSI Design - A Circuits and Systems Perspective" 3ed.  Overview, Geiger, Allen, Strader "VLSI Design techniques for analog and digital circuits" McGraw-Hill Device sizing, Sutherland,Sproull and Harris, "Logical Effort: Designing Fast CMOS Circuits" Wiring & timing, Dally and Poulton "Digital Systems Engineering" Advanced processing, Chang and Sze "ULSI Technology".  

      Mode of delivery

      • Face to face

      Type of Teaching Activity/Activities

      • Cours magistraux
      • Exercices dirigés
      • Utilisation de logiciels
      • Travaux pratiques
      • Travaux de laboratoire

      Evaluations

      The assessment methods of the Learning Activity (AA) are specified in the course description of the corresponding Educational Component (UE)

      (*) HT : Hours of theory - HTPE : Hours of in-class exercices - HTPS : hours of practical work - HD : HMiscellaneous time - HR : Hours of remedial classes. - Per. (Period), Y=Year, Q1=1st term et Q2=2nd term
      Date de génération : 13/07/2020
      20, place du Parc, B7000 Mons - Belgique
      Tél: +32 (0)65 373111
      Courriel: info.mons@umons.ac.be